high speed cmos logic ? 54HC02 quad 2-input nor gates in bare die form ? output drive capability: 10 lsttl loads ? low input current: 1a ? outputs directly inter face cmos, nmos and ttl ? die size (unsawn) 610 x 610 24 x 24 m mils minimum bond pad size 85 x 85 3.35 x 3.35 m mils die thickness 350 (20) 13.78 (0.79) m mils top metal composition al 1%si 1.1m back metal composition n/a C bare si ? operating voltage range: 2v to 6v ? function compatible with 54ls02 ? high noise immunity cmos process ? full military temperature range. rev 1.0 22/04/19 features: description the 54HC02 2-input nor gat e is fabricated on a .35m advanced cmos process combining high speed lsttl performance with cmos low power. the device performs the boolean function y = (a + b) or y = a ? b in positive logic. internal circuitry c omprises of thre e stages and includes buffered output for high noise immunity and stability. inputs are compatible with standard cmos outputs; with pull-up resistors , they are compatible with lsttl outputs. the product die size is significantly smaller than industry peers due to its re-design and production using a more advanced cmos process. ordering information die dimensions in m (mils) the following part suffixes apply: ? no suffix - mil-std-883 /2010b visual inspection ? h - mil-std-883 /2010b visual inspection + mil-prf-38534 class h lat ? k - mil-std-883 /2010a visual inspection (space) + mil-prf-38534 class k lat lat = lot acceptance test. 610 (24) 610 (24) for further information on la t process flows see below. www.siliconsupplies. com\quality\bare-die-lot-qualification supply formats: mechanical specification ? default C die in waffle pack (400 per tray capacity) ? sawn wafer on tape C on request ? unsawn wafer C on request ? die thickness <> 350m(14 mils) C on request ? assembled into ceramic package C on request page 1 of 5 www.siliconsupplies.com a l l d a t a s h e e t . c o m
d high speed cmos logic ? 54HC02 rev 1.0 22/04/19 coordinates (m) pad function x y 1 1y -230 -52 2 1a -230 -230 3 1b -95 -230 4 2y 0 -230 5 2a 95 -230 6 2b 230 -230 7 gnd 230 -45 8 3a 230 95 9 3b 230 230 10 3y 95 230 11 4a 0 230 12 4b -220 230 13 4y -230 140 14 v cc -230 45 connect chip back to v cc or float pad layout and functions logic diagram 610m (24 mils) 610m (24 mils) 0,0 pad 14 = v cc pad 7 = gnd 10 11 12 13 9 8 14 7 1 2 3 4 5 6 truth table inputs output a b y l l h h l h l h h l l l h = high level (steady state) l = low level (steady state) page 2 of 5 www.siliconsupplies.com a l l d a t a s h e e t . c o m
page 3 of 5 www.siliconsupplies.com high speed cmos logic ? 54HC02 rev 1.0 22/04/19 parameter symbol min max units supply voltage v cc 2 6 v dc input or output voltage v in ,v out 0 v cc v operating temperature range t a -55 +125 c v cc = 2v 0 1000 v cc = 4.5v 0 500 input rise or fall times t r , t f v cc = 6.0v 0 400 ns recommended operating conditions 2 (voltages referenced to gnd) absolute maximum ratings 1 parameter symbol value unit dc supply voltage (referenced to gnd) v cc -0.5 to +7.0 v dc input voltage (referenced to gnd) v in -0.5 to v cc +0.5 v dc output voltage (referenced to gnd) v out -0.5 to v cc +0.5 v dc input current i in 20 ma dc output current, per pad i out 25 ma dc supply current, v cc or gnd i cc 50 ma power dissipation in still air p d 750 mw storage temperature range t stg -65 to 150 c 2. this device contains protecti on circuitry to guard against dama ge due to high static voltages or electric fields. however, pr ecautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance ci rcuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic vo ltage level (e.g., either gnd or v cc ). unused outputs must be left open. dc electrical characteristics (voltages referenced to gnd) 1. operation above the absolute maxi mum rating may cause device fa ilure. operation at the absolute maximum ratings, for extended periods, may reduce device reliability. limits parameter symbol v cc conditions -55c to 25 c 85c 125c units 2.0v 1.5 1.5 1.5 3.0v 2.1 2.1 2.1 4.5v 3.15 3.15 3.15 minimum high-level input voltage v ih 6.0v v out = 0.1v or v cc -0.1v i out 20a 4.2 4.2 4.2 v 2.0v 0.5 0.5 0.5 3.0v 0.9 0.9 0.9 4.5v 1.35 1.35 1.35 maximum low-level input voltage v il 6.0v v out = 0.1v or v cc -0.1v i out 20a 1.8 1.8 1.8 v a l l d a t a s h e e t . c o m
high speed cmos logic ? 54HC02 dc electrical characteristics continued (voltages referenced to gnd) rev 1.0 22/04/19 limits parameter 3. not production tested in die form , characterized by chip design and tested in package lat. 4. used to determine the no-load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . symbol v cc conditions 125c units -55c to 25c 85c 2.0v 1.9 1.9 1.9 4.5v 4.4 4.4 4.4 6.0v v in = v ih or v il i out 20a 5.9 5.9 5.9 v 3.0v v in = v ih or v il i out 2.4ma 2.48 2.34 2.20 4.5v v in = v ih or v il i out 4.0ma 3.98 3.84 3.70 minimum high-level output voltage v oh 6.0v v in = v ih or v il i out 5.2ma 5.48 5.34 5.20 v 2.0v 0.1 0.1 0.1 4.5v 0.1 0.1 0.1 6.0v v in = v il or v il i out 20a 0.1 0.1 0.1 v 3.0v v in = v il or v il i out 2.4ma 0.26 0.33 0.40 4.5v v in = v il or v il i out 4.0ma 0.26 0.33 0.40 maximum low-level output voltage v ol v v in = v il or v il 6.0v i out 5.2ma 0.26 0.33 0.40 maximum input leakage current i in 6.0v v in = v cc or gnd 0.1 1.0 1.0 a maximum quiescent v in = v cc or gnd supply leakage current 3 i cc 6.0v i out = 0a 1 10 40 a a c electrical characteristics 3 limits parameter symbol v cc conditions units -55c to 25c 85c 125c 2.0v 75 95 110 3.0v 30 40 55 4.5v 15 19 22 maximum propagation delay, input a or b to c l = 50pf, output y (figure 1,2) t plh, t phl ns t r = t f = 6ns 6.0v 13 16 19 2.0v 75 95 110 3.0v 30 40 55 4.5v 15 19 22 maximum output rise and fall time, c l = 50pf, any output (figure 1,2) t tlh, t thl ns t r = t f = 6ns 6.0v 13 16 19 page 4 of 5 www.siliconsupplies.com a l l d a t a s h e e t . c o m
page 5 of 5 www.siliconsupplies.com high speed cmos logic ? 54HC02 rev 1.0 22/04/19 a c electrical characteristics continued 3 limits parameter disclaimer: the information given in this document shall in no event be reg arded as a guarantee of conditions or characteristics. with re spect to any examples or hints given herei n, any typical values stated h erein and/or any information r egarding the application of the d evice, silicon supplies ltd hereby disclaims any and all warranties and liabilities of any kind. life support policy : silicon supplies ltd components may be used in life support dev ices or systems only with the express written approval of silicon supplies ltd, if a failure of such componen ts can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted i n the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. switchin g waveform dut c l * output test point test circuit * includes all probe and jig capacitance figure 1 C propagation delay & output transition time figure 2 symbol v cc conditions units -55c to 25c 85c 125c maximum input capacitance c in - - 10 10 10 pf typical power dissipation t a = 25c, pf capacitance per gate 4 c pd - v cc =5.0v 22 3. not production tested in die fo rm, characterized by chip de sign and tested in package lat. 4. used to determine the no-load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . a l l d a t a s h e e t . c o m
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